功率半导体器件基础 英文版【2025|PDF下载-Epub版本|mobi电子书|kindle百度云盘下载】

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Chapter 1 Introduction1

1.1 Ideal and Typical Power Switching Waveforms3

1.2 Ideal and Typical Power Device Characteristics5

1.3 Unipolar Power Devices8

1.4 Bipolar Power Devices10

1.5 MOS-Bipolar Power Devices11

1.6 Ideal Drift Region for Unipolar Power Devices14

1.7 Charge-Coupled Structures:Ideal Specific On-Resistance16

1.8 Summary21

Problems21

References22

Chapter 2 Material Properties and Transport Physics23

2.1 Fundamental Properties23

2.1.1 Intrinsic Carrier Concentration25

2.1.2 Bandgap Narrowing26

2.1.3 Built-in Potential30

2.1.4 Zero-Bias Depletion Width32

2.1.5 Impact Ionization Coefficients32

2.1.6 Carrier Mobility34

2.2 Resistivity51

2.2.1 Intrinsic Resistivity51

2.2.2 Extrinsic Resistivity51

2.2.3 Neutron Transmutation Doping55

2.3 Recombination Lifetime59

2.3.1 Shockley-Read-Hall Recombination60

2.3.2 Low-Level Lifetime63

2.3.3 Space-Charge Generation Lifetime65

2.3.4 Recombination Level Optimization66

2.3.5 Lifetime Control75

2.3.6 Auger Recombination80

2.4 Ohmic Contacts82

2.5 Summary84

Problems84

References86

Chapter 3 Breakdown Voltage91

3.1 Avalanche Breakdown92

3.1.1 Power Law Approximations for the Impact Ionization Coefficients92

3.1.2 Multiplication Coefficient94

3.2 Abrupt One-Dimensional Diode95

3.3 Ideal Specific On-Resistance100

3.4 Abrupt Punch-Through Diode101

3.5 Linearly Graded Junction Diode104

3.6 Edge Terminations107

3.6.1 Planar Junction Termination108

3.6.2 Planar Junction with Floating Field Ring120

3.6.3 Planar Junction with Multiple Floating Field Rings130

3.6.4 Planar Junction with Field Plate132

3.6.5 Planar Junction with Field Plates and Field Rings137

3.6.6 Bevel Edge Terminations137

3.6.7 Etch Terminations148

3.6.8 Junction Termination Extension149

3.7 Open-Base Transistor Breakdown155

3.7.1 Composite Bevel Termination159

3.7.2 Double-Positive Bevel Termination159

3.8 Surface Passivation162

3.9 Summary162

Problems163

References164

Chapter 4 Schottky Rectifiers167

4.1 Power Schottky Rectifier Structure168

4.2 Metal-Semiconductor Contact169

4.3 Forward Conduction171

4.4 Reverse Blocking179

4.4.1 Leakage Current180

4.4.2 Schottky Barrier Lowering181

4.4.3 Prebreakdown Avalanche Multiplication184

4.4.4 Silicon Carbide Rectifiers185

4.5 Device Capacitance187

4.6 Thermal Considerations188

4.7 Fundamental Tradeoff Analysis192

4.8 Device Technology194

4.9 Barrier Height Adjustment194

4.10 Edge Terminations197

4.11 Summary198

Problems199

References200

Chapter 5 P-i-N Rectifiers203

5.1 One-Dimensional Structure204

5.1.1 Recombination Current205

5.1.2 Low-Level Injection Current206

5.1.3 High-Level Injection Current208

5.1.4 Injection into the End Regions217

5.1.5 Carrier-Carrier Scattering Effect219

5.1.6 Auger Recombination Effect219

5.1.7 Forward Conduction Characteristics221

5.2 Silicon Carbide P-i-N Rectifiers230

5.3 Reverse Blocking232

5.4 Switching Performance236

5.4.1 Forward Recovery236

5.4.2 Reverse Recovery244

5.5 P-i-N Rectifier Structure with Buffer Layer262

5.6 Nonpunch-Through P-i-N Rectifier Structure263

5.7 P-i-N Rectifier Tradeoff Curves270

5.8 Summary274

Problems275

References276

Chapter 6 Power MOSFETs279

6.1 Ideal Specific On-Resistance280

6.2 Device Cell Structure and Operation282

6.2.1 The V-MOSFET Structure283

6.2.2 The VD-MOSFET Structure284

6.2.3 The U-MOSFET Structure285

6.3 Basic Device Characteristics286

6.4 Blocking Voltage289

6.4.1 Impact of Edge Termination289

6.4.2 Impact of Graded Doping Profile290

6.4.3 Impact of Parasitic Bipolar Transistor291

6.4.4 Impact of Cell Pitch293

6.4.5 Impact of Gate Shape296

6.4.6 Impact of Cell Surface Topology298

6.5 Forward Conduction Characteristics300

6.5.1 MOS Interface Physics301

6.5.2 MOS Surface Charge Analysis305

6.5.3 Maximum Depletion Width310

6.5.4 Threshold Voltage311

6.5.5 Channel Resistance321

6.6 Power VD-MOSFET On-Resistance327

6.6.1 Source Contact Resistance329

6.6.2 Source Region Resistance330

6.6.3 Channel Resistance331

6.6.4 Accumulation Resistance332

6.6.5 JFET Resistance333

6.6.6 Drift Region Resistance335

6.6.7 N+ Substrate Resistance339

6.6.8 Drain Contact Resistance339

6.6.9 Total On-Resistance340

6.7 Power VD-MOSFET Cell Optimization343

6.7.1 Optimization of Gate Electrode Width343

6.7.2 Impact of Breakdown Voltage345

6.7.3 Impact of Design Rules348

6.7.4 Impact of Cell Topology350

6.8 Power U-MOSFET On-Resistance358

6.8.1 Source Contact Resistance359

6.8.2 Source Region Resistance361

6.8.3 Channel Resistance361

6.8.4 Accumulation Resistance362

6.8.5 Drift Region Resistance363

6.8.6 N+ Substrate Resistance364

6.8.7 Drain Contact Resistance365

6.8.8 Total On-Resistance365

6.9 Power U-MOSFET Cell Optimization368

6.9.1 Orthogonal P-Base Contact Structure368

6.9.2 Impact of Breakdown Voltage371

6.9.3 Ruggedness Improvement372

6.10 Square-Law Transfer Characteristics373

6.11 Superlinear Transfer Characteristics377

6.12 Output Characteristics381

6.13 Device Capacitances385

6.13.1 Basic MOS Capacitance386

6.13.2 Power VD-MOSFET Structure Capacitances389

6.13.3 Power U-MOSFET Structure Capacitances399

6.13.4 Equivalent Circuit408

6.14 Gate Charge409

6.14.1 Charge Extraction409

6.14.2 Voltage and Current Dependence417

6.14.3 VD-MOSFET vs.U-MOSFET Structure421

6.14.4 Impact of VD-MOSFET and U-MOSFET Cell Pitch423

6.15 Optimization for High Frequency Operation426

6.15.1 Input Switching Power Loss427

6.15.2 Output Switching Power Loss432

6.15.3 Gate Propagation Delay434

6.16 Switching Characteristics436

6.16.1 Turn-On Transient437

6.16.2 Turn-Off Transient440

6.16.3 Switching Power Losses443

6.16.4 [dV/dt] Capability443

6.17 Safe Operating Area447

6.17.1 Bipolar Second Breakdown449

6.17.2 MOS Second Breakdown451

6.18 Integral Body Diode452

6.18.1 Reverse Recovery Enhancement453

6.18.2 Impact of Parasitic Bipolar Transistor453

6.19 High-Temperature Characteristics454

6.19.1 Threshold Voltage454

6.19.2 On-Resistance455

6.19.3 Saturation Transconductance456

6.20 Complementary Devices457

6.20.1 The p-Channel Structure458

6.20.2 On-Resistance458

6.20.3 Deep-Trench Structure459

6.21 Silicon Power MOSFET Process Technology460

6.21.1 Planar VD-MOSFET Process460

6.21.2 Trench U-MOSFET Process462

6.22 Silicon Carbide Devices465

6.22.1 The Baliga-Pair Configuration465

6.22.2 Planar Power MOSFET Structure476

6.22.3 Shielded Planar Power MOSFET Structures481

6.22.4 Shielded Trench-Gate Power MOSFET Structure489

6.23 Summary498

Problems499

References503

Chapter 7 Bipolar Junction Transistors507

7.1 Power Bipolar Junction Transistor Structure508

7.2 Basic Operating Principles510

7.3 Static Blocking Characteristics513

7.3.1 Open-Emitter Breakdown Voltage514

7.3.2 Open-Base Breakdown Voltage514

7.3.3 Shorted Base-Emitter Operation516

7.4 Current Gain520

7.4.1 Emitter Injection Efficiency522

7.4.2 Emitter Injection Efficiency with Recombination in the Depletion Region526

7.4.3 Emitter Injection Efficiency with High-Level Injection in the Base528

7.4.4 Base Transport Factor533

7.4.5 Base Widening at High Collector Current Density536

7.5 Emitter Current Crowding550

7.5.1 Low-Level Injection in the Base551

7.5.2 High-Level Injection in the Base555

7.5.3 Emitter Geometry559

7.6 Output Characteristics560

7.7 On-State Characteristics565

7.7.1 Saturation Region566

7.7.2 Quasisaturation Region571

7.8 Switching Characteristics574

7.8.1 Turn-On Transition575

7.8.2 Turn-Off Transition588

7.9 Safe Operating Area607

7.9.1 Forward-Biased Second Breakdown608

7.9.2 Reverse-Biased Second Breakdown611

7.9.3 Boundary for Safe Operating Area615

7.10 Darlington Configuration616

7.11 Summary619

Problems619

References621

Chapter 8 Thyristors625

8.1 Power Thyristor Structure and Operation628

8.2 Blocking Characteristics631

8.2.1 Reverse-Blocking Capability632

8.2.2 Forward-Blocking Capability636

8.2.3 Cathode Shorting641

8.2.4 Cathode Shorting Geometry644

8.3 On-State Characteristics651

8.3.1 On-State Operation652

8.3.2 Gate-Triggering Current654

8.3.3 Holding Current657

8.4 Switching Characteristics662

8.4.1 Turn-On Time663

8.4.2 Gate Design671

8.4.3 Amplifying Gate Design672

8.4.4 [dV/dt]Capability675

8.4.5 Turn-Off Process683

8.5 Light-Activated Thyristors685

8.5.1 [dI/dt]Capability686

8.5.2 Gate Region Design687

8.5.3 Optically Generated Current Density688

8.5.4 Amplifying Gate Design690

8.6 Self-Protected Thyristors691

8.6.1 Forward Breakdown Protection691

8.6.2 [dV/dt]Turn-On Protection694

8.7 The Gate Turn-Off Thyristor Structure698

8.7.1 Basic Structure and Operation698

8.7.2 One-Dimensional Tum-Off Criterion701

8.7.3 One-Dimensional Storage Time Analysis703

8.7.4 Two-Dimensional Storage Time Model704

8.7.5 One-Dimensional Voltage Rise Time Model706

8.7.6 One-Dimensional Current Fall Time Model709

8.7.7 Switching Energy Loss721

8.7.8 Maximum Turn-Off Current722

8.7.9 Cell Design and Layout725

8.8 The Triac Structure726

8.8.1 Basic Structure and Operation728

8.8.2 Gate-Triggering Mode 1729

8.8.3 Gate-Triggering Mode 2730

8.8.4 [dV/dt]Capability731

8.9 Summary733

Problems733

References735

Chapter 9 Insulated Gate Bipolar Transistors737

9.1 Basic Device Structures741

9.2 Device Operation and Output Characteristics745

9.3 Device Equivalent Circuit748

9.4 Blocking Characteristics748

9.4.1 Symmetric Structure Forward-Blocking Capability748

9.4.2 Symmetric Structure Reverse-Blocking Capability753

9.4.3 Symmetric Structure Leakage Current754

9.4.4 Asymmetric Structure Forward-Blocking Capability760

9.4.5 Asymmetric Structure Reverse-Blocking Capability767

9.4.6 Asymmetric Structure Leakage Current769

9.5 On-State Characteristics776

9.5.1 On-State Model776

9.5.2 On-State Carrier Distribution:Symmetric Structure783

9.5.3 On-State Voltage Drop:Symmetric Structure791

9.5.4 On-State Carrier Distribution:Asymmetric Structure796

9.5.5 On-State Voltage Drop:Asymmetric Structure803

9.5.6 On-State Carrier Distribution:Transparent Emitter Structure808

9.5.7 On-State Voltage Drop:Transparent Emitter Structure813

9.6 Current Saturation Model815

9.6.1 Carrier Distribution:Symmetric Structure820

9.6.2 Output Characteristics:Symmetric Structure828

9.6.3 Output Resistance:Symmetric Structure833

9.6.4 Carrier Distribution:Asymmetric Structure834

9.6.5 Output Characteristics:Asymmetric Structure844

9.6.6 Output Resistance:Asymmetric Structure848

9.6.7 Carrier Distribution:Transparent Emitter Structure849

9.6.8 Output Characteristics:Transparent Emitter Structure853

9.6.9 Output Resistance:Transparent Emitter Structure855

9.7 Switching Characteristics856

9.7.1 Turn-On Physics:Forward Recovery857

9.7.2 Turn-Off Physics:No-Load Conditions865

9.7.3 Turn-Off Physics:Resistive Load867

9.7.4 Turn-Off Physics:Inductive Load876

9.7.5 Energy Loss per Cycle904

9.8 Power Loss Optimization907

9.8.1 Symmetric Structure907

9.8.2 Asymmetric Structure909

9.8.3 Transparent Emitter Structure911

9.8.4 Comparison of Tradeoff Curves912

9.9 Complementary(P-Channel)Structure913

9.9.1 On-State Characteristics915

9.9.2 Switching Characteristics919

9.9.3 Power Loss Optimization919

9.10 Latch-Up Suppression920

9.10.1 Deep P+ Diffusion922

9.10.2 Shallow P+ Layer928

9.10.3 Reduced Gate Oxide Thickness931

9.10.4 Bipolar Current Bypass936

9.10.5 Diverter Structure939

9.10.6 Cell Topology943

9.10.7 Latch-Up Proof Structure948

9.11 Safe Operating Area951

9.11.1 Forward-Biased Safe Operating Area952

9.11.2 Reverse-Biased Safe Operating Area956

9.11.3 Short-Circuit Safe Operating Area960

9.12 Trench-Gate Structure966

9.12.1 Blocking Mode967

9.12.2 On-State Carrier Distribution969

9.12.3 On-State Voltage Drop971

9.12.4 Switching Characteristics973

9.12.5 Safe Operating Area974

9.12.6 Modified Structures978

9.13 Blocking Voltage Scaling980

9.13.1 N-Base Design981

9.13.2 Power MOSFET Baseline982

9.13.3 On-State Characteristics982

9.13.4 Tradeoff Curve985

9.14 High Temperature Operation986

9.14.1 On-State Characteristics986

9.14.2 Latch-Up Characteristics989

9.15 Lifetime Control Techniques991

9.15.1 Electron Irradiation991

9.15.2 Neutron Irradiation993

9.15.3 Helium Irradiation993

9.16 Cell Optimization994

9.16.1 Planar-Gate Structure995

9.16.2 Trench-Gate Structure999

9.17 Reverse Conducting Structure1006

9.18 Summary1014

Problems1015

References1020

Chapter 10 Synopsis1027

10.1 Typical H-Bridge Topology1027

10.2 Power Loss Analysis1029

10.3 Low DC Bus Voltage Applications1032

10.4 Medium DC Bus Voltage Applications1037

10.5 High DC Bus Voltage Applications1041

10.6 Summary1045

Problems1045

References1047

Index1049